Study of the Interface Microstructure of Sn-Ag-Cu Lead-Free Solders and the Effect of Solder Volume on Intermetallic Layer Formation

Although the primary driver for the current interest in developing lead-free soldering is global market pressure for more environmentally friendly products, the main concern continues to be lead contamination from end-of-life electronic products in landfill sites. In response to existing and impending legislation in Europe and Japan for the elimination of lead from electronic products, the industry has embarked on a number of studies in search of suitable lead-free alternatives. Several reports [1,2] have been published, but there are as yet no drop-in solutions with respect to reflow temperature, joint reliability and assembly costs. Our survey show that the SnAg-Cu alloy is one of the promising lead-free alloys currently being evaluated by industry. There are however a number of issues regarding the use of Sn-Ag-Cu alloys, including the solderability and long-term reliability of the solder joints, which require further study. The lower solderability of Sn-AgCu solder can alter the interface and microstructure of the solder joint formed because of the differing reaction rates between the molten solder and substrate surface. This also has an impact on the nature and extent of the intermetallic compounds formed at the interface, as the intermetallic is generally more brittle than the base metal. This can negatively impact the solder joint reliability. In this paper we report a study on the effect of solder volume on intermetallic layer formation and thickness. For lead-free soldering this could prove to be very important, as a wide range of devices and components of varying joint size, e.g. plastic quad flat pack (PQFP), ball grid array (BGA), chip-scale packaging (CSP), and flip chip, may need to be assembled on a typical board. This means that the nature and thickness of the intermetallic layer formed for each joint size will be different. In the study, solder joints of different sizes representing different devices were used for evaluating the effect of solder volume on intermetallic compound formation. The layer thickness and microstructure were analyzed using scanning electron microscopy (SEM). SEM analysis was also carried out on joint micro-sections, which has undergone temperature cycling to evaluate the effect of intermetallic layer the joint reliability. Our results show that increasing the solder volume (and solder joint size) does not significantly affect the growth of the intermetallic layer thickness. Therefore the intermetallic layer thickness provides the lower limit for solder joint design for ultra-fine pitch flip-chip applications.